The present invention relates to a semiconductor integrated circuit (LSI) as well as a D-A converter device and an A-D converter device, and more particularly, to a technique for increasing the relative accuracy between a plurality of capacitances in an LSI chip.
Generally, when a plurality of capacitor cells are formed in a semiconductor integrated circuit, the relative accuracy is determined by the degree of uniformity of the insulating layer between two electrodes that forms each capacitor cell, and in addition, the degree of uniformity of parasitic capacitances formed by the wirings by which the electrodes are connected to another circuit element. In order to avoid variations due to the shapes of devices, n unit capacitor cells are connected in parallel when a capacitance that is n times (n is an integer) that of a unit capacitance C is required.
In addition, when a desired capacitance is obtained by combining unit capacitor cells in a capacitor array, the unit capacitor cells are selected from the capacitor array in a distributive manner, taking into variations between the unit capacitor cells in the capacitor array. For example, assuming that capacitors having a capacitance ratio of C1:C2:C3=1:1:2 are required, a unit capacitor cell 100A and a unit capacitor cell 100B are respectively assigned for the capacitance C1 and the capacitance C2 and two unit capacitor cells 100C and 100D are assigned for the capacitance C3.
In this case, a lower electrode wiring 300 is connected in common to all the lower electrodes 200A to 200D of the unit capacitor cells 100A to 100D, and is arranged along the peripheral edge of the capacitor array. An upper electrode wiring 500A connected to an upper electrode 400A of the unit capacitor cell 100A is arranged along the lower electrode wiring 300, whereas an upper electrode wiring 500C for the unit capacitor cells 100C and 100D is arranged to pass through the vicinity of the unit capacitor cells 100A to 100D. With this arrangement, parasitic capacitances 600 are apt to be produced particularly by the upper electrode wirings 500A and 500C. In order to avoid these, it is necessary to ensure wide spaces between the capacitor cells 100A to 100D.
If the spaces between the capacitor cells 100A to 100D are widened, however, capacitance value variations between the capacitor cells 100A to 100D increase in the capacitor array, resulting in degradation in the relative accuracy of the capacitances between the capacitor cells 100A to 100D. Moreover, the area of the capacitor array as a whole increases, leading to an increase in chip cost.
The following discusses how much area is required for a capacitor array in a case of a 10-bit charge distribution type D-A converter that has a capacitor array composed of a plurality of unit capacitor cells. It should be noted that in the following discussion, the capacitor array is as follows. Four unit capacitor cells are disposed in a 2×2 arrangement, and each unit cell has a pair of electrodes formed by interposing an insulating layer (relative dielectric constant: 4) between a conductive layer (thickness: 1 μm) and a conductive layer dedicated to a capacitor electrode, and is a square in which each side is 14 μm. The capacitance density is 1 fF/ μm2 (unit capacitance: 196 fF). The wirings have a wire width of 0.5 μm and are formed in the conductive layer.
In this case, the parasitic capacitance that is generated when a wiring is disposed between unit capacitor cells at a certain distance L (unit: μm) from each of the unit capacitor cell is calculated using opposing area capacitance conversion approximately as follows:14×1×(1/L)×4×8.85E−18=0.5 fF/L 
Meanwhile, it is necessary in this case that the relative accuracy of the capacitance of the most significant bit is less than 0.05% of the unit capacitance (196 fF).
Accordingly, in order to reduce the parasitic capacitance to less than 0.05% of the unit capacitance, it is necessary that the distance L between the unit capacitor cell and the wiring should be:0.5 fF/L<196 fF×0.0005,and thus,L>5.1 μm.In this case, the area required by this capacitor array needs to be:(14×2+5.1×2+0.5)2=38.72=1497.69,and thus, it is understood that this capacitor array requires approximately twice the area of the case in which four unit capacitor cells are merely arranged without providing spaces therebetween (28×28=784).
In addition, when two wirings are disposed between unit capacitor cells and the spaces for these wirings are also need to be spaced apart in a similar manner, the spaces between unit capacitor cells is 16.3 μm. Under this condition, if the capacitor array has 36 unit capacitor cells that are arrayed in a 6×6 arrangement, the area of the capacitor array as a whole becomes approximately four times the area that is effectively used as capacitors.
As described above, the prior art has at least the drawbacks as follows. When parasitic capacitances due to wiring are taken into consideration in order to avoid degradation in relative accuracy of the capacitances of capacitor cells, a large space between capacitor cells is necessitated, which consequently degrades the relative accuracy of the capacitances between the plurality of capacitor cells. Moreover, a larger device area is necessitated, which leads to an increase in chip cost.